Dynamic random-access memories (DRAMs) provide the bulk of the semiconductor-based memories on most computer systems. A DRAM stores data in the form of charge that is stored on a capacitor within the memory cell. The current commercially available DRAMs store one bit in each memory cell, which consists of a transistor and a capacitor. The cost per bit stored is determined by the size of the memory cell. Hence, the prior art has achieved cost reductions in DRAMs by reducing the size of the transistor and capacitor.
A second method for reducing the cost of DRAM storage is to utilize memory cells that can store multiple bits per memory cell. To store N bits per memory cell, each memory cell must provide 2.sup.N discrete distinguishable states. In general, the states correspond to the charge stored on a capacitor. The maximum number of bits that can be stored depends on the sensitivity of the circuits used to measure the stored charge and on the ability of the write circuits to precisely control the amount of charge that is stored on the capacitor. Prior art multilevel DRAMS have been limited to two or three bits per storage cell.
The amount of charge that leaks off of the capacitor is a non-linear function of the amount of charge that was stored on the capacitor during programming. To compensate for the charge leakage, reference cells that are written at the same time as the storage cells are programmed with predetermined data values. Hence, the size of a "word" that stores M bits of data must be increased by the number of reference cells needed to read the data in that word. At the time the data is read from the storage cells, it is compared to the values in the reference cells. If the number of storage levels is relatively small, a reference cell can be included for each possible data value. However, this strategy fails if the number of storage levels is high. For example, if each storage cell stores 8 bits, than each word would require 256 reference cells. Any savings realized by storing multiple bits per memory cell would be consumed by the additional reference cells.
Broadly, it is the object of the present invention to provide an improved multilevel DRAM memory.
It is a further object of the present invention to provide a DRAM memory that does not require one reference cell per storage level.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.